Test circuitry is often included within a semiconductor device die so that self test procedures can be utilized after manufacture of the semiconductor device die. Having self test circuitry built into the semiconductor device die often improves test cycle time; however, this self test circuitry consumes a portion of the die area thereby increasing the size for the resulting semiconductor package for the die. Further, this self test circuit can also require externally accessible test connection pads that are electrically active, and these test pads can lead to misuse by customers. For example, a semiconductor die can include one or more pins on a package that are only used during test procedures. These test-only pins can lead to incorrect use or treatment by end customers that lead to device failures. Further, even when properly grounded by the end customer, such test-only pins still must meet full ESD (electro-static discharge) and latch-up requirements for external pins in order to achieve customer qualification. Thus, while it is efficient for test purposes to include test circuitry within the semiconductor die, this on-chip test circuitry can require increased die and package sizes and lead to problems from customer misuse.
A plurality of semiconductor device die are typically formed on a semiconductor substrate. A seal ring around each die provides a protective metal barrier for the internal device circuitry within the die, such as test circuitry. The seal ring is formed using metal layers and metal vias through dielectric layers that lie between the metal layers. The structures for the seal ring are formed during semiconductor processing steps used to form the device circuitry for the semiconductor device die. One or more cuts will be made through scribe lines to singulate the semiconductor device die once the semiconductor processing steps for the semiconductor substrate are completed.
When one or more cuts are made within the scribe lane to singulate the semiconductor die, the seal ring structures will be left at the edge of the die to form a protective metal barrier that extends from the surface of the die to the substrate. It is again noted that seal ring structures are typically used for protective purposes, such as to reduce edge cracks, to reduce ionic contamination, and/or to serve other protective purposes.
In addition to seal ring structures, bond pads are typically formed on the die that can be used to connect active circuitry in the die to external components. One type of connection is referred to as a wirebond. To form a wirebond, a wire is held in a bonding tool while a free air ball (FAB) is formed at the end of wire by electrical flame-off that heats the end of wire to a malleable state. The FAB is then lowered to contact the bond pad, compressed, and subjected to ultrasonic generation (USG). The vibration of the USG effectively scrubs the FAB against the aluminum bond pad, promoting interdiffusion of the metal of the FAB and the metal of the bond pad, creating a conductive intermetallic compound. It is often found that the forces generated during wirebonding in technologies also utilizing low-k inter-layer dielectrics (ILD) are susceptible to wire bond delamination or ILD cracking.
Pillar connections may also be employed as a means of attaching the die to a substrate or another die. Pillar connections are typically created through several deposition, plating, photolithography and etch steps. The pillars commonly include a copper post with a solder tip. Similar to wirebond connections, pillar connections can result in forces from thermocompression bonding or due to thermal coefficient of expansion mismatches which can result in excessive stress on the bond pad below the pillar. The excessive stress can cause pad delamination or ILD cracking.